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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. copyright ? cirrus logic, inc. 2005 (all rights reserved) cirrus logic, inc. http://www.cirrus.com features z four 24-bit a/d, six 24-bit d/a converters z adc dynamic range ? 105 db differential ? 102 db single-ended z dac dynamic range ? 108 db differential ? 105 db single-ended z adc/dac thd+n ? -98 db differential ? -95 db single-ended z compatible with industry-standard time division multiplexed (t dm) serial interface z dac sampling rates up to 192 khz z adc sampling rates up to 96 khz z programmable adc high-pass filter for dc offset calibration z logarithmic digital volume control z hardware mode or software i2c & spi ? z supports logic levels between 5 v and 1.8 v general description the cs42432 codec provides four multi-bit analog-to-dig- ital and six multi-bit digital-to-analog delta-sigma converters. the codec is capable of operation with either differential or single-ended inputs and outputs, in a 52 -pin m qfp package. four fully differential, or single-ended, inputs are available on stereo adc1and adc 2 . digital volume control is provid- ed for each adc channel, with selectable overflow detection. all six dac channels provide digital volume control and can operate with differential or single-ended outputs. an auxiliary serial input is available for an additional two channels of pcm data. the cs42432 is ideal for audio systems requiring wide dy- namic range, negligible distortion and low noise, such as a/v receivers, dvd receivers, and automotive audio systems. ordering information see page 59 . control port & serial audio port supply = 1.8 v to 5 v register configuration internal voltage reference reset tdm serial interface level translator level translator tdm serial audio input digital supply = 3.3 v hardware mode or i 2 c/spi software mode control data analog supply = 3.3 v to 5 v differential or single-ended outputs 6 input master clock 6 tdm serial audio output multibit oversampling adc1 high pass filter differential or single-ended analog inputs 2 digital filters 2 multibit oversampling adc2 high pass filter 2 digital filters 2 auxilliary serial audio input volume controls digital filters multibit dac1-3 and analog filters ? modulators cs42432 feb ?05 ds673pp2 108 db, 192 khz 4-in, 6-out tdm codec
2 ds673pp2 table of contents 1 pin description - software mode ................................................................................ 6 1.1 digital i/o pin characteristics ........................................................................................... .7 2 pin descriptions - hardware mode ............................................................................ 8 3 typical connection diagrams .................................................................................... 10 4 characteristics and specifications ....................................................................... 12 specified operating conditions . .............. ................ ............. ............. ............. ......... 12 absolute maximum ratings ...... ................ ................ ................ ............. ............. ......... 12 analog input characteristics (cs42432-cmz)....................................................... 13 analog input characteristics (cs42432-dmz)....................................................... 14 adc digital filter characteristics ......................................................................... 15 analog output characteristics (cs42432 -cmz)................................................... 16 analog output characteristics (cs42432 -dmz)................................................... 18 combined dac interpolation & on-chip analog filter response ................ 20 switching specifications - adc/dac port .............................................................. 21 switching characteristics - aux port................................................................... 22 switching specifications - control port - i2c mode......................................... 23 switching specifications - control port - spi format ................................... 24 dc electrical characteristics................................................................................. 25 digital interface specifications & chara cteristics ....................................... 25 5 applications ............................................................................................................... ........ 26 5.1 overview .................................................................................................................. ........ 26 5.2 analog inputs ............................................................................................................. ...... 27 5.2.1 line level inputs ................................................................................................. 27 5.2.2 high pass filter and dc offset calib ration ....................................................... 27 5.3 analog outputs ............................................................................................................ .... 28 5.3.1 initialization ......................................................................................................... 2 8 5.3.2 line-level outputs and filtering .......................................................................... 28 5.3.3 digital volume control ..................... ................................................................... 30 5.3.4 de-emphasis filter .............................................................................................. 30 5.4 system clocking ........................................................................................................... ... 31 5.5 codec digital interface .................................................................................................. 3 1 5.5.1 tdm .................................................................................................................... 3 1 5.5.2 i/o channel allocation ........................................................................................ 32 5.6 aux port digital interface formats .................................................................................. 33 5.6.1 i2s ..................................................................................................................... ... 33 5.6.2 left justified ........................................................................................................ 33 5.7 control port descrip tion and timing ................................................................................ 34 5.7.1 spi mode ............................................................................................................ 34 5.7.2 i 2 c mode ............................................................................................................. 35 5.8 recommended power-up sequence ............... ................................................................ 36 5.8.1 hardware mode ................................................................................................... 36 5.8.2 software mode .................................................................................................... 36 5.9 reset and power-up ....................................................................................................... 36 5.10 power supply, grou nding, and pcb layout ................................................................... 37 6 register quick reference ........................................................................................... 38 7 register description ..................................................................................................... 40 7.1 memory address pointer (map) ....................................................................................... 40 7.2 chip i.d. and revision register (address 01h) (read only) ............................................ 40 7.3 power control (address 02h) ............................................................................................ 41 7.4 functional mode (address 03h) ........................................................................................ 42 7.5 miscellaneous control (address 04h) ............................................................................... 42
ds673pp2 3 7.6 adc control & dac de-empha sis (address 05h) ............................................................ 43 7.7 transition control (address 06h) ................ ...................................................................... 44 7.8 dac channel mute (address 07h) ................ ................................................................... 45 7.9 aoutx volume control (addresses 08h-0d) ............................................................... 45 7.10 dac channel invert (address 10h) ................................................................................ 46 7.11 ainx volume control (address 11h-14h) . ...................................................................... 46 7.12 adc channel invert (address 17h) ................................................................................ 47 7.13 status (address 19h) (read only)................................................................................. 47 7.14 status mask (address 1ah) ............................................................................................ 47 8 appendix a: external filters ...................................................................................... 49 8.1 adc input filter ..................................... ..................................................................... ..... 49 8.1.1 passive input filter ............................................................................................. 50 8.1.2 passive input filter w/attenuation ....................................................................... 50 8.2 dac output filter ......................................................................................................... ... 51 9 appendix b: adc filter plots ....................................................................................... 52 10 appendix c: dac filter pl ots ........... ................. ................ ................ ................ ......... 54 11 parameter definitions ................................................................................................. 56 12 references ................................................................................................................ ....... 57 13 package information ................................................................................................... 58 13.1 thermal characteristics ................................................................................................ 58 14 ordering information ................................................................................................. 59 15 revision history .......................................................................................................... ... 60
4 ds673pp2 list of figures figure 1. typical connection diagram (softwar e mode) .............................................................. 10 figure 2. typical connection diagram (hardwar e mode) ............................................................. 11 figure 3. output test load ..................................................................................................... ...... 19 figure 4. maximum loading....... ............................................................................................... .... 19 figure 5. tdm serial audio interface timing ...... .......................................................................... 21 figure 6. serial audio interface slave mode ti ming ..................................................................... 22 figure 7. control port timing - i2c format.................................................................................... 2 3 figure 8. control port timing - spi format...... ............................................................................. 24 figure 9. full-scale input ..................................................................................................... ......... 27 figure 10. audio output initialization flow char t .......................................................................... 29 figure 11. full-scale output ................................................................................................... ...... 30 figure 12. de-emphasis curve ........................... ........................................................................ .. 31 figure 13. tdm serial audio format................... .......................................................................... 32 figure 14. aux i2s format...................................................................................................... ...... 33 figure 15. aux left justified format ........................................................................................... .33 figure 16. control port timing in spi mode..... ............................................................................. 34 figure 17. control port timing, i2c write ......... ............................................................................. 35 figure 18. control port timing, i2c read...................................................................................... 3 5 figure 19. single to differential active input filter ........................................................................ 49 figure 20. single-ended active input filter................................................................................... 4 9 figure 21. passive input filter ................................................................................................ ....... 50 figure 22. passive input filter w/attenuation................................................................................ 50 figure 23. active analog output filter ............. ............................................................................ .51 figure 24. passive analog output filter........... ............................................................................. 51 figure 25. ssm stopband rejection ....................... ...................................................................... 5 2 figure 26. ssm transition band ... .............................................................................................. .. 52 figure 27. ssm transition band (d etail)....................................................................................... 5 2 figure 28. ssm passband ripple ....................... .......................................................................... 52 figure 29. dsm stopband rejection............................................................................................. 5 2 figure 30. dsm transition band ................................................................................................. .. 52 figure 31. dsm transition band (detail) ...................................................................................... 53 figure 32. dsm passband ripple ................................................................................................. 53 figure 33. ssm stopband rejection ....................... ...................................................................... 5 4 figure 34. ssm transition band ... .............................................................................................. .. 54 figure 35. ssm transition band (d etail) ....................................................................................... 5 4 figure 36. ssm passband ripple ....................... .......................................................................... 54 figure 37. dsm stopband rejection............................................................................................. 5 4 figure 38. dsm transition band ................................................................................................. .. 54 figure 39. dsm transition band (detail) ....................................................................................... 5 5 figure 40. dsm passband ripple ................................................................................................. 55 figure 41. qsm stopband rejection............................................................................................. 5 5 figure 42. qsm transition band................................................................................................. .. 55 figure 43. qsm transition band (detail)....................................................................................... 5 5 figure 44. qsm passband ripple........................... ...................................................................... 55
ds673pp2 5 list of tables table 1. i/o power rails....................................................................................................... ................. 7 table 2. hardware config urable settings........................................................................................ .... 26 table 3. mclk frequency settings............................................................................................... ...... 31 table 4. serial audio interface channel allocations ........................................................................... 3 2 table 5. mclk frequency settings............................................................................................... ...... 42 table 7. example ain volume settings .............. ............................................................................. ... 46 table 6. example aout volume settings .......................................................................................... 46 table 8. revision history...................................................................................................... ............... 60
6 ds673pp2 1 pin description - software mode pin name # pin description scl/cclk 1 serial control port clock ( input ) - serial clock for the control port interface. sda/cdout 2 serial control data i/o ( input/output ) - input/output for i 2 c data. output for spi data. ad0/cs 3 address bit [0]/ chip select ( input ) - chip address bit in i 2 c mode. control signal used to select the chip in spi mode. ad1/cdin 4 address bit [1]/ spi data input ( input ) - chip address bit in i 2 c mode. input for spi data. rst 5 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. vlc 6 control port power ( input ) - determines the required signal level for the control port interface. see ?digital i/o pin characteristics? on page 7. fs 7 frame sync ( input ) - signals the start of a new tdm frame in the tdm digital interface format. vd 8 digital power ( input ) - positive power supply for the digital section. dgnd 9,18 digital ground ( input ) - vls 10 serial port interface power ( input ) - determines the required signal level for the serial port inter- faces. see ?digital i/o pin characteristics? on page 7. sclk 11 serial clock (input) - serial clock for the se rial audio interface. input frequency must be 256xfs. mclk 12 master clock ( input ) - clock source for the delta-sigma modulators and digital filters. adc_sdout 13 serial audio data output (output) - tdm output for two?s complement serial audio data. dac_sdin 14 dac serial audio data input ( input ) - tdm input for tw o?s complement serial audio data. aux_lrck 15 auxiliary left/right clock ( output ) - determines which channel, left or right, is currently active on the auxiliary serial audio data line. 6 2 4 8 10 1 3 5 7 9 11 12 14 15 16 17 18 19 20 21 22 23 24 25 33 37 35 31 29 38 36 34 32 30 28 27 52 51 50 49 48 47 46 45 44 43 42 41 vls fs mclk vlc filt+ n.c. aout5+ aout3+ agnd va aux_sdin dac_sdin adc_sdout aux_sclk aux_lrck aout4+ rst aout6+ aout3- va agnd aout2+ aout2- aout1- aout1+ dgnd vd sclk dgnd vq n.c. n.c. aout6- aout4- 13 26 39 aout5- 40 n.c. n.c. n.c. ain3+ ain4- ain4+ n.c. ain3- n.c. ain1+ ain2- ain2+ ain1- scl/cclk ad1/cdin ad0/cs sda/cdout cs42432
ds673pp2 7 1.1 digital i/o pin characteristics various pins on the cs42432 are powered from separat e power supply rails. the logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings. aux_sclk 16 auxiliary serial clock (output) - serial clock for the auxi liary serial audio interface. aux_sdin 17 auxiliary serial input ( input ) - the cs42432 provides an additional serial input for two?s comple- ment serial audio data. aout1 +,- aout2 +,- aout3 +,- aout4 +,- aout5 +,- aout6 +,- 20,19 21,22 24,23 25,26 28,27 29,30 differential analog output ( output ) - the full-scale differential anal og output level is specified in the analog characteristics specification table. each positive leg of the differential outputs may also be used single-ended. n.c. 31,32 33,34 49,50 51,52 not connected - do not connect. agnd 35,48 analog ground ( input ) - vq 36 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. va 37,46 analog power ( input ) - positive power supply for the analog section. ain1 +,- ain2 +,- ain3 +,- ain4 +,- 39,38 41,40 43,42 45,44 differential analog input ( input ) - signals are presented differentia lly to the delta-sigma modula- tors. the full-scale input level is specified in the analog characteristics specification table. filt+ 47 positive voltage reference ( output ) - positive referenc e voltage for the internal sampling cir- cuits. power rail pin name sw/(hw) i/o driver receiver vlc rst input - 1.8 v - 5.0 v, cmos scl/cclk (test) input - 1.8 v - 5.0 v, cmos, with hysteresis sda/cdout (test) input/ output 1.8 v - 5.0 v, cmos/open drain 1.8 v - 5.0 v, cmos, with hysteresis ad0/cs (mfreq) input - 1.8 v - 5.0 v, cmos ad1/cdin (test) input - 1.8 v - 5.0 v, cmos vls mclk input - 1.8 v - 5.0 v, cmos lrck input - 1.8 v - 5.0 v, cmos sclk input - 1.8 v - 5.0 v, cmos adc_sdout (adc3_single) input/ output 1.8 v - 5.0 v, cmos - dac_sdin input - 1.8 v - 5.0 v, cmos aux_lrck output 1.8 v - 5.0 v, cmos - aux_sclk output 1.8 v - 5.0 v, cmos - aux_sdin input - 1.8 v - 5.0 v, cmos table 1. i/o power rails
8 ds673pp2 2 pin descriptions - hardware mode pin name # pin description test 1,2,4 test ( input ) - must be tied high or low. do not leave unconnected. mfreq 3 mclk frequency ( input ) - sets the required frequency range of the input master clock. see sec- tion 5.4 for the appropriate settings. rst 5 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. vlc 6 control port power ( input ) - determines the required signal level for the control port interface. see ?digital i/o pin characteristics? on page 7. fs 7 frame sync ( input ) - signals the start of a new tdm frame in the tdm digital interface format. vd 8 digital power ( input ) - positive power supply for the digital section. vls 10 serial port interface power ( input ) - determines the required signal level for the serial port inter- faces. sclk 11 serial clock (input) - serial clock for the se rial audio interface. input frequency must be 256xfs. adc_sdout 13 serial audio data output (output) - tdm output for two?s complement serial audio data. dac_sdin 14 dac serial audio data input ( input ) - input for two?s complement serial audio data. aux_lrck 15 auxiliary left/right clock ( output ) - determines which channel, left or right, is currently active on the auxiliary serial audio data line. aux_sclk 16 auxiliary serial clock (output) - serial clock for the auxi liary serial audio interface. aux_sdin 17 auxiliary serial input ( input ) - the cs42432 provides an additional serial input for two?s comple- ment serial audio data. test 6 2 4 8 10 1 3 5 7 9 11 12 14 15 16 17 18 19 20 21 22 23 24 25 33 37 35 31 29 38 36 34 32 30 28 27 52 51 50 49 48 47 46 45 44 43 42 41 vls fs mclk vlc test filt+ n.c. aout5+ aout3+ agnd va aux_sdin dac_sdin adc_sdout aux_sclk aux_lrck mfreq aout4+ rst aout6+ aout3- va agnd aout2+ aout2- aout1- aout1+ dgnd vd sclk dgnd vq aout6- aout4- 13 test 26 39 aout5- 40 n.c. n.c. n.c. ain3+ ain4- ain4+ ain3- ain1+ ain2- ain2+ ain1- n.c. n.c. n.c. n.c. cs42432
ds673pp2 9 aout1 +,- aout2 +,- aout3 +,- aout4 +,- aout5 +,- aout6 +,- 20,19 21,22 24,23 25,26 28,27 29,30 differential analog output ( output ) - the full-scale differential anal og output level is specified in the analog characteristics specification table. each positive leg of the differential outputs may also be used single-ended. n.c. 31,32 33,34 49,50 51,52 not connected - do not connect. agnd 35,48 analog ground ( input ) - vq 36 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. va 37,46 analog power ( input ) - positive power supply for the analog section. ain1 +,- ain2 +,- ain3 +,- ain4 +,- 39,38 41,40 43,42 45,44 differential analog input ( input ) - signals are presented differentia lly to the delta-sigma modula- tors. the full-scale input level is specified in the analog characteristics specification table. filt+ 47 positive voltage reference ( output ) - positive referenc e voltage for the internal sampling cir- cuits.
10 ds673pp2 3 typical connection diagrams 100 f 0.1 f + + vq filt+ 0.1 f 4.7 f va 0.01 f dgnd digital audio processor cs5341 a/d converter va vd agnd agnd connect dgnd and agnd at codec 0.01 f + 10 f 0.01 f +3.3 v + 10 f 0.01 f +1.8 v to +5.0 v 1. see the adc input filter section in the appendix. 2. see the dac output filter section in the appendix. +3.3 v to +5 v dgnd aout1+ aout1- aout2+ aout2- aout3+ aout3- aout4+ aout4- analog output filter 2 analog output filter 2 analog output filter 2 aout5+ aout5- aout6+ aout6- analog output filter 2 analog output filter 2 analog output filter 2 0.1 f +1.8 v to +5 v micro- controller 2 k ? 2 k ? ** ** ** resistors are required for i 2 c control port operation analog input 1 analog input 2 ain3+ ain1+ ain1- ain2+ ain2- ain3- ain4+ ain4- analog input 3 analog input 4 input filter 1 input filter 1 input filter 1 input filter 1 17 16 10 15 13 14 7 11 12 5 6 9 48 35 18 47 37 44 45 42 43 40 41 38 39 30 29 27 28 26 25 23 24 22 21 19 20 46 37 8 1 2 4 3 vls mclk aux_sdin dac_sdin fs sclk aux_sclk aux_lrck adc_sdout vlc scl/cclk rst ad0/cs sda/cdout ad1/cdin figure 1. typical connecti on diagram (software mode)
ds673pp2 11 100 f 0.1 f + + vq filt+ 0.1 f 4.7 f va 0.01 f dgnd 0.1 f digital audio processor cs5341 a/d converter va vd agnd agnd connect dgnd and agnd at codec 0.01 f + 10 f 0.01 f +3.3 v + 10 f 0.01 f +1.8 v to +5.0 v 1. see the adc input filter section in the appendix. 2. see the dac output filter section in the appendix. analog input 1 analog input 2 ain3+ +3.3 v to +5 v dgnd ain1+ ain1- ain2+ ain2- ain3- ain4+ ain4- analog input 3 analog input 4 input filter 1 aout1+ aout1- aout2+ aout2- aout3+ aout3- aout4+ aout4- analog output filter 2 analog output filter 2 analog output filter 2 aout5+ aout5- aout6+ aout6- analog output filter 2 analog output filter 2 analog output filter 2 input filter 1 input filter 1 input filter 1 17 16 10 15 13 14 7 11 12 3 5 6 9 48 35 18 47 37 44 45 42 43 40 41 38 39 30 29 27 28 26 25 23 24 22 21 19 20 46 37 8 vlc rst mfreq vls mclk aux_sdin dac_sdin fs sclk aux_sclk aux_lrck adc_sdout figure 2. typical connection diagram (hardware mode)
12 ds673pp2 4 characteristics and specifications (all min/max characteristics and specifications are guarante ed over the specified operat ing conditions. typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and t a = 25 c.) specified operat ing conditions (agnd=dgnd=0 v, all voltages with respect to ground.) absolute maximum ratings (agnd = dgnd = 0 v; all volt ages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. analog input/outpu t performance will slightly degrade at va = 3.3 v. 2. the adc_sdout may not meet timing requirements in double-speed mode. 3. any pin except supplies. transient currents of up to 100 ma on the ana log input pins will not cause scr latch-up. 4. the maximum over/under voltage is limited by the input current. parameters symbol min typ max units dc power supply analog 3.3 v (note 1) 5.0 v va 3.14 4.75 3.3 5 3.47 5.25 v v digital 3.3 v vd 3.14 3.3 3.47 v serial audio interface 1.8 v (note 2) 2.5 v 3.3 v 5.0 v vls 1.71 2.37 3.14 4.75 1.8 2.5 3.3 5 1.89 2.63 3.47 5.25 v v v v control port interface 1.8 v 2.5 v 3.3 v 5.0 v vlc 1.71 2.37 3.14 4.75 1.8 2.5 3.3 5 1.89 2.63 3.47 5.25 v v v v ambient temperature commercial -cmz automotive -dmz t a -10 -40 - - +70 +85 c c parameters symbol min max units dc power supply analog digital serial port interface control port interface va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 v v v v input current (note 3) i in -10ma analog input voltage (note 4) v in agnd-0.7 va+0.7 v digital input voltage serial port interface (note 4) control port interface v ind-s v ind-c -0.3 -0.3 vls+ 0.4 vlc+ 0.4 v v ambient operating temperature cs42432-cmz (power applied) cs42432-dmz t a -20 -50 +85 +95 c c storage temperature t stg -65 +150 c
ds673pp2 13 analog input character istics (cs42432-cmz) (test conditions (unless otherwise specified): vls = vlc = vd = 3.3 v, va = 5 v; full scale input sine wave: 1 khz through the active input filter on page 49; measurement ba ndwidth is 10 hz to 20 khz un less otherwise specified.) differential single-ended parameter min typ max min typ max unit single speed mode fs=48 khz dynamic range a-weighted unweighted 99 96 105 102 - - 96 93 102 99 - - db db total harmonic distortion + noise -1 db (note 5) -20 db -60 db - - - -98 -82 -42 -92 - - - - - -95 -79 -39 -89 - - db db db double speed mode fs=96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 99 96 - 105 102 99 - - - 96 93 102 99 96 - - - db db db total harmonic distortion + noise -1 db (note 5) -20 db -60 db 40 khz bandwidth -1 db - - - - -98 -82 -42 -90 -92 - - - - - - - -95 -79 -39 -90 -89 - - - db db db db all speed modes adc1-2 interchannel isolation - 90 - - 90 - db dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - 100 - - 100 - ppm/c analog input full-scale input voltage 1.06*va 1.12*va 1.18*va 0.53*va 0.56*va 0.59*va vpp differential input impedance (note 6) 18 - - - - - k ? single-ended input impedance (note 7) ---18--k ? common mode rejection ratio (cmrr) - 82 - - - - db
14 ds673pp2 analog input character istics (cs42432-dmz) (test conditions (unless otherwise specified):vls = vlc = vd = 3.3 v, va = 5 v; full scale input sine wave: 1 khz through the active input filter on page 49; measurement ba ndwidth is 10 hz to 20 khz un less otherwise specified.) notes: 5. referred to the typical full-scale voltage. 6. measured between ainx+ and ainx-. 7. measured between ainxx and agnd. differential single-ended parameter min typ max min typ max unit single speed mode fs=48 khz dynamic range a-weighted unweighted 97 94 105 102 - - 94 91 102 99 - - db db total harmonic distortion + noise -1 db (note 5) -20 db -60 db - - - -98 -82 -42 -90 - - - - - -95 -79 -39 -87 - - db db db double speed mode fs=96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 97 94 - 105 102 99 - - - 94 91 - 102 99 96 - - - db db db total harmonic distortion + noise -1 db (note 5) -20 db -60 db 40 khz bandwidth -1 db - - - - -98 -82 -42 -87 -90 - - - - - - - -95 -79 -39 -87 -87 - - - db db db db all speed modes adc1-2 interchannel isolation - 90 - - 90 - db dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - 100 - - 100 - ppm/c analog input full-scale input voltage 1.04*va 1.12*va 1.20*va 0.52*va 0.56*va 0.60*va vpp differential input impedance (note 6) 18 - - - - - k ? single-ended input impedance (note 7) ---18--k ? common mode rejection ratio (cmrr) - 82 - - - - db
ds673pp2 15 adc digital filter characteristics notes: 8. filter response is guaranteed by design. 9. response is clock dependent and will sca le with fs. note that the re sponse plots (figures 25 to 32) have been normalized to fs and can be de-normalized by multiplying the x- axis scale by fs. parameter (note 8, 9) min typ max unit single speed mode (note 9) passband (frequency response) to -0.1 db corner 0 - 0.4896 fs passband ripple - - 0.08 db stopband 0.5688 - - fs stopband attenuation 70 - - db total group delay - 12/fs - s double speed mode (note 9) passband (frequency response) to -0.1 db corner 0 - 0.4896 fs passband ripple - - 0.16 db stopband 0.5604 - - fs stopband attenuation 69 - - db total group delay - 9/fs - s high pass filter characteristics frequency response -3.0 db -0.13 db -1 20 - - hz hz phase deviation @ 20 hz - 10 - deg passband ripple - - 0 db filter settling time - 10 5 /fs 0 s
16 ds673pp2 analog output characteristics (cs42432-cmz) (test conditions (unless otherwise s pecified):vls = vlc = vd = 3.3 v, va = 5 v; measurement bandwidth is 10 hz to 20 khz unless otherwise specif ied; full scale 997 hz output sine wave (see note 11); single-ended test load: r l = 3 k ? , c l = 10 pf.) parameter differential min typ max single-ended min typ max unit single-speed mode fs = 48 khz dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 102 99 - - 108 105 99 96 - - - - 99 96 - - 105 102 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -98 -85 -45 -93 -76 -36 -92 - - - - - - - - - - -95 -82 -42 -90 -73 -33 -89 - - - - - db db db db db db double-speed mode fs = 96 khz dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 102 99 - - 108 105 99 96 - - - - 99 96 - - 105 102 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -98 -85 -45 -93 -76 -36 -92 - - - - - - - - - - -95 -82 -42 -90 -73 -33 -89 - - - - - db db db db db db quad-speed mode fs = 192 khz dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 102 99 - - 108 105 99 96 - - - - 99 96 - - 105 102 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -98 -85 -45 -93 -76 -36 -92 - - - - - - - - - - -95 -82 -42 -90 -73 -33 -89 - - - - - db db db db db db
ds673pp2 17 all speed modes interchannel isolation (1 khz) - 100 - - 100 - db analog output full scale output 1.235?va 1.300?va 1.3 65?va 0.618?va 0.650?va 0.683?va vpp interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c output impedance - 100 - - 100 - ? dc current draw from an aout pin (note 10) --10--10 a ac-load resistance (r l ) (note 12) 3--3--k ? load capacitance (c l ) (note 12) - - 100 - - 100 pf
18 ds673pp2 analog output characteristics (cs42432-dmz) (test conditions (unless otherwise specified): vls = vl c = vd = 3.3 v,va = 5 v; measurement bandwidth is 10 hz to 20 khz unless otherwise specif ied; full scale 997 hz output sine wave (see note 11); single-ended test load: r l = 3 k ? , c l = 10 pf.) parameter differential min typ max single-ended min typ max unit single-speed mode fs = 48 khz dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 100 97 - - 108 105 99 96 - - - - 97 94 - - 105 102 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -98 -85 -45 -93 -76 -36 -90 - - - - - - - - - - - -95 -82 -42 -90 -73 -33 -87 - - - - - db db db db db db double-speed mode fs = 96 khz dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 100 97 - - 108 105 99 96 - - - - 97 94 - - 105 102 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -98 -85 -45 -93 -76 -36 -90 - - - - - - - - - - - -95 -82 -42 -90 -73 -33 -87 - - - - - db db db db db db quad-speed mode fs = 192 khz dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 100 97 - - 108 105 99 96 - - - - 97 94 - - 105 102 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -98 -85 -45 -93 -76 -36 -90 - - - - - - - - - - - -95 -82 -42 -90 -73 -33 -87 - - - - - db db db db db db
ds673pp2 19 notes: 10. guaranteed by design. the dc current draw represents the allowed current draw from the aout pin due to typical leakage through the el ectrolytic dc blocking capacitors. 11. one-half lsb of triangular pdf dither is added to data. 12. guaranteed by design. see figure 3. r l and c l reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. in this circuit topology, c l will effectively move the dominant pole of the two-po le amp in the output stage. increasing this value beyond the recommended 100 pf can caus e the internal op-amp to become unstable. see appendix a for a recommended output filter. all speed modes interchannel isolation (1 khz) - 100 - - 100 - db analog output full scale output 1.210?va 1.300?va 1.3 92?va 0.605?va 0.650?va 0.696?va vpp interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c output impedance - 100 - - 100 - ? dc current draw from an aout pin (note 10) --10--10 a ac-load resistance (r l ) (note 12) 3--3--k ? load capacitance (c l ) (note 12) - - 100 - - 100 pf 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20 aoutxx 3.3 f analog output c l + r l dac1-3 agnd figure 3. output test load figure 4. maximum loading
20 ds673pp2 combined dac interpolation & on -chip analog filt er response notes: 13. response is clock dependent and w ill scale with fs. note that the response plots (figures 33 to 44) have been normalized to fs and can be de-normalized by multiplying the x- axis scale by fs. 14. single and double speed mode measurement bandwidth is from stopband to 3 fs. quad speed mode measurement bandwidth is from stopband to 1.34 fs. 15. de-emphasis is only available in single speed mode. parameter (note 8, 13) min typ max unit single speed mode passband (frequency response) to -0.05 db corner to -3 db corner 0 0 - - 0.4780 0.4996 fs fs frequency response 10 hz to 20 khz -0.2 - +0.08 db stopband 0.5465 - - fs stopband attenuation (note 14) 50 - - db group delay - 10/fs - s de-emphasis error (note 15) fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - +1.5/+0 +0.05/-0.25 -0.2/-0.4 db db db double speed mode passband (frequency response) to -0.1 db corner to -3 db corner 0 0 - - 0.4650 0.4982 fs fs frequency response 10 hz to 20 khz -0.2 - +0.7 db stopband 0.5770 - - fs stopband attenuation (note 14) 55 - - db group delay - 5/fs - s quad speed mode passband (frequency response) to -0.1 db corner to -3 db corner 0 0 - - 0.397 0.476 fs fs frequency response 10 hz to 20 khz -0.2 - +0.05 db stopband 0.7 - - fs stopband attenuation (note 14) 51 - - db group delay - 2.5/fs - s
ds673pp2 21 switching specificatio ns - adc/dac port (inputs: logic 0 = dgnd, logic 1 = vls, adc_sdout c load = 15 pf.) notes: 16. after powering up the cs42432, rst should be held low after the powe r supplies and clocks are settled. 17. see table 5 on page 42 for suggested mclk frequencies. 18. vls is limited to nominal 2.5 v to 5.0 v operation only. 19. adc does not meet timing spec ification for quad-speed mode. parameters symbol min max units slave mode rst pin low pulse width (note 16) 1-ms mclk frequency 0.512 50 mhz mclk duty cycle (note 17) 45 55 % input sample rate (fs pin) single-speed mode double-speed mode (note 18) quad-speed mode (note 19) f s f s f s 4 50 100 50 100 200 khz khz khz sclk duty cycle 45 55 % sclk high time t sckh 8-ns sclk low time t sckl 8-ns fs rising edge to sclk rising edge t fss 5-ns sclk rising edge to fs falling edge t fsh 16 - ns dac_sdin setup time be fore sclk rising edge t ds 3-ns dac_sdin hold time after sclk rising edge t dh 5-ns dac_sdin hold time after sclk rising edge t dh1 5-ns adc_sdout hold time after sclk rising edge t dh2 10 - ns adc_sdout valid before sclk rising edge t dval 15 - ns adc_sdout dac_sdin t ds sclk (input) fs (input) msb t dh1 t sckh t sckl t dval msb-1 msb msb-1 t fsh t fss t dh2 figure 5. tdm serial audio interface timing
22 ds673pp2 switching characteris tics - aux port (inputs: logic 0 = dgnd, logic 1 = vls.) parameters symbol min max units master mode output sample rate (a ux_lrck) all speed modes f s - lrck khz aux_sclk frequency - 64 lrck khz aux_sclk duty cycle 45 55 % aux_lrck edge to sclk rising edge t lcks -5ns aux_sdin setup time be fore sclk rising edge t ds 3-ns aux_sdin hold time after sclk rising edge t dh 5-ns aux_sdin aux_sclk aux_lrck t sckh t sckl t lcks t ds msb t dh msb-1 figure 6. serial audio interface slave mode timing
ds673pp2 23 switching specifications - control port - i2c mode (vlc = 1.8 v - 5.0 v, vls = vd = 3.3 v, va = 5.0 v; inputs: logic 0 = dgnd, logic 1 = vlc, sda c l =30pf) notes: 20. data must be held for sufficient time to brid ge the transition time, t fc , of scl. 21. guaranteed by design. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 20) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda (note 21) t rc -1s fall time scl and sda (note 21) t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t low t hdd t high t sud stop start sda scl t irs rst t hdst t rc t fc t sust t sus p start stop repeated t rd t fd t ack figure 7. control port timing - i2c format
24 ds673pp2 switching specifications - co ntrol port - spi format (vlc = 1.8 v - 5.0 v, vls = vd = 3.3 v, va = 5.0 v; inputs: logic 0 = dgnd, logic 1 = vlc, cdout c l =30pf) notes: 22. data must be held fo r sufficient time to bridge the transition time of cclk. 23. for f sck <1 mhz. parameter symbol min max units cclk clock frequency f sck 06.0mhz rst rising edge to cs falling t srs 20 - ns cs falling to cclk edge t css 20 - ns cs high time between transmissions t csh 1.0 - s cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 22) t dh 15 - ns cclk falling to cdout stable t pd -50ns rise time of cdout t r1 -25ns fall time of cdout t f1 -25ns rise time of cclk and cdin (note 23) t r2 - 100 ns fall time of cclk and cdin (note 23) t f2 - 100 ns cs cclk cdin cdout rst t srs t scl t sch t css t r2 t f2 t csh t dsu t dh msb msb t pd figure 8. control port timing - spi format
ds673pp2 25 dc electrical characteristics (agnd = 0 v; all voltages with respect to ground.) notes: 24. normal operation is defined as rst = hi with a 997 hz, 0 dbfs input to the dac and aux port, and a 1 khz, -1 db analog input to the adc port sampled at the highest f s for each speed mode. dac outputs are open, unless otherwise specified. 25. i dt measured with no external loading on pin (sda). 26. valid with the recommended capa citor values on filt+ and vq. in creasing the capacitance will also increase the psrr. 27. power down mode is defined as rst = lo with all clocks and data li nes held static and no analog input. 28. guaranteed by design. the dc current draw represen ts the allowed current draw from the vq pin due to typical leakage through the electrolytic de-coupling capacitors. digital interface specific ations & characteristics notes: 29. see ?digital i/o pin characteristics? on page 7 for serial and control port power rails. parameters symbol min typ max units normal operation (note 24) power supply current va = 5.0 v vls = vlc = vd = 3.3 v (note 25) i a i dt - - 80 60.6 - - ma ma power dissipation vls = vlc = vd = 3.3 v,5 v - 600 850 mw power supply rejection ratio 1 khz (note 26) 60 hz psrr - - 60 40 - - db db power-down mode (note 27) power dissipation vls = vlc = vd = 3.3 v,va = 5 v - 1.25 - mw vq characteristics nominal voltage output impedance dc current source/sink (note 28) - - - 0.5?va 23 - - - 10 v k ? a filt+ nominal voltage - va - v parameters (note 29) symbol min typ max units high-level output voltage at i o =2 ma serial port control port v oh vls-1.0 vlc-1.0 - - - - v v low-level output voltage at i o =2 ma serial port control port v ol - - - - 0.4 0.4 v v high-level input voltage serial port control port v ih 0.7xvls 0.7xvlc - - - - v v low-level input voltage serial port control port v il - - - - 0.2xvls 0.2xvlc v v input leakage current i in --10 a input capacitance (note 21) - - 10 pf
26 ds673pp2 5 applications 5.1 overview the cs42432 is a highly integrated mixed signal 24- bit audio codec comprised of 4 analog-to-digital converters (adc), implemented using multi-bit delt a-sigma techniques, and 6 digital-to-analog converters (dac) also implemented using multi-bit delta-sigma techniques. other functions integrated within the codec incl ude independent digital volume controls for each dac, digital de-emphasis filters for the dac, digital volu me control with gain on each adc channel, adc high- pass filters, and an on-chip voltage reference. the serial audio interface ports allow up to 6 da c channels and 6 adc channels in a time-division mul- tiplexed (tdm) interface format. the cs42432 features an auxiliary port used to accommodate an addi- tional two channels of pcm data on the adc_sdout data line in the tdm digital interface format. see ?aux port digital interface formats? on page 33 for details. the cs42432 operates in one of three oversampling modes based on the input sample rate. mode selec- tion is determined automatically based on the mclk frequency setting. single-speed mode (ssm) sup- ports input sample rates up to 50 khz and uses a 128x oversampling ratio. double-speed mode (dsm) supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode (qsm) supports input sample rates up to 200 khz an d uses an oversampling ratio of 32x (note: qsm for the adc is only supported in the i2s, left-justified, right-justified interface formats. qsm is not sup- ported for the adc). note: qsm is only available in software mode (see section 5.4 on page 31 for de- tails). all functions can be configured through software via a serial control port operable in spi mode or in i2c mode. a hardware, stand-alone mode is also available, allowing confi guration of the codec on a more limited basis. see table 2 for the default configuration in hardware mode. figure 1 on page 10 and figure 2 on page 11 show the recommended connections for the cs42432 in software and hardware mode, respectively. see sectio n ?register description? on page 40 for the default register settings and options in software mode. hardware mode feature summary function default configuration hardware control note power down adc all adc?s are enabled - - power down dac all dac?s are enabled - - power down device device is powered up - - mclk frequency select selectable between 256fs and 512fs ?mfreq? pin 3 see section 5.4 freeze control n/a - - aux serial port interfac e format left-justified - - adc1/adc2 high pass filter free ze high pass filter is always enabled -- dac de-emphasis no de-emphasis applied - - adc1/adc2 single-ended mode disabled - - dac volume control/mute/inver t all dac volume = 0 db, un- muted, not inverted -- adc volume control all adc volume = 0 db - - dac soft ramp/zero cross immediate change - - table 2. hardware configurable settings
ds673pp2 27 5.2 analog inputs 5.2.1 line level inputs ainx+ and ainx- are the line level differential analog inputs internally biased to vq, approxi- mately va/2. figure 9 on page 27 shows the full-scale analog input levels. the cs42432 also accommodates single-ended signals on all inpu ts, ain1-ain4. see ?adc input filter? on page 49 for the recommended input filters. hardware mode ain volume control and adc overflow status are not accessible in hardware mode. software mode for single-ended operation on adc1-adc2 (ain1 to ain4), the adcx_single bit in the regis- ter ?adc control & dac de-emphasis (address 05h)? on page 43 must be set appropriately (see figure 20 on page 49 for required external components). the gain/attenuation of the signal can be adjusted for each ainx independently through the ?ainx volume control (address 11h-14h)? on page 46. the adc output data is in 2?s comple- ment binary format. for inputs above positive full sc ale or below negative full scale, the adc will output 7fffffh or 800000h, respectively and caus e the adc overflow bit in the register ?sta- tus (address 19h) (read only)? on page 47 to be set to a ?1?. 5.2.2 high pass filter and dc offset calibration the high pass filter continuously subtracts a measure of the dc offset from the output of the dec- imation filter. if the high pass filter is disabl ed during normal operation, the current value of the dc offset for the corresponding channel is frozen and this dc offset will continue to be subtract- adc soft ramp/zero cross immediate change - - dac auto-mute enabled - - status interrupt n/a - - hardware mode feature summary function default configuration hardware control note table 2. hardware configurable settings full-scale differential input level = (ainx+) - (ainx-) = 5.6 v pp = 1.98 v rms ainx+ ainx- 3.9 v 2.5 v 1.1 v 5.0 v 3.9 v 2.5 v 1.1 v va figure 9. full-scale input
28 ds673pp2 ed from the conversion result. this feature makes it possible to perform a system dc offset cal- ibration by: 1) running the cs42432 with the high pass filter en abled until the filter settles. see the digital filter characteristics for filter settling time. 2) disabling the high pass filter and freezing the stored dc offset. hardware mode the high pass filters for adc1 and adc2 are permanently enabled in hardware mode. software mode the high pass filter for adc1/adc2 can be enabled and disabled. the high pass filters are con- trolled using the hpf_freeze bit in the regi ster ?adc control & dac de-emphasis (address 05h)? on page 43. 5.3 analog outputs 5.3.1 initialization the initialization and power-down sequence flow chart is shown in figure 10 on page 29. the cs42432 enters a power-down state upon initial power-up. the interpolation & decimation fil- ters, delta-sigma modulators and control port regi sters are reset. the internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor low-pass fil- ters are powered down. the device will remain in the power-down state until the rst pin is brought high. the control port is accessible once rst is high and the desired register settings can be loaded per the in- terface descriptions in the ?control port desc ription and timing? on page 34. in hardware mode operation, the hardware mode pins must be setup before rst is brought high. all features will default to the hardware mode defaults as listed in table 2. once mclk is valid, vq will quickly charge to va/2, and the internal volt age reference, filt+, will begin powering up to normal operation. power is applied to the d/a converters and switched- capacitor filters, and the analog outputs are clamped to the quiescent voltage, vq. once lrck is valid, mclk occurrences are counted over one lrck period to determine the mclk/lrck fre- quency ratio. after an approximate 2000 sample period delay, normal operation begins. 5.3.2 line-level outputs and filtering the cs42432 contains on-chip buffer amplifiers capable of producing line level differential as well as single-ended outputs on aout1-aout6. thes e amplifiers are biased to a quiescent dc level of approximately vq. the delta-sigma conversion process produ ces high frequency noise beyond the audio pass- band, most of which is removed by the on-chip analog filters. the remaining out-of-band noise can be attenuated using an off-chip low pass filter. see ?dac output filter? on page 51 for recommended output filter. the active filter configuration accounts for the normally differing ac loads on the aoutx+ and aoutx- differential output pins. also shown is a passive filter configuration which minimizes costs and the number of compo- nents. figure 11 shows the full-scale analog output levels . all outputs are internally biased to vq, ap- proximately va/2.
ds673pp2 29 no power 1. vq = ? 2. aout bias = ? 3. no audio signal generated. control port accessed control port access detected? valid mclk applied? valid mclk applied? no pdn bit = '1'b? sub-clocks applied 1. lrck valid. 2. sclk valid. 3. audio samples processed. valid mclk/lrck ratio? no yes yes no yes no yes no yes yes no normal operation 1. vq = va/2. 2. aout bias = va/2. 3. audio signal generated per register settings. analog output freeze 1. vq = va/2. 2. aout bias = va/2 + last audio sample. 3. no audio signal generated. analog output mute 1. vq = va/2. 2. aout bias = va/2. 3. no audio signal generated. error: mclk/lrck ratio change error: mclk removed rst = low error: power removed pdn bit set to '1'b software mode registers setup to desired settings. hardware mode h/w pins setup to desired settings. rst = low? 2000 lrck delay power-up 1. vq = va/2. 2. aout bias = vq. power-down 1. vq discharge to 0 v. 2. aout bias = hi-z. 3. no audio signal generated. 4. control port registers retain settings. power-down (power applied) 1. vq = 0 v. 2. aout = hi-z. 3. no audio signal generated. 4. control port registers reset to default. figure 10. audio output initialization flow chart
30 ds673pp2 5.3.3 digital volume control hardware mode dac volume control and mute are not accessible in hardware mode. software mode each dac?s output level is controlled via the volume control registers operating over the range of 0 to -127.5 db attenuation with 0.5 db resolution. see ?aoutx volume control (addresses 08h-0d)? on page 45. volume control changes are programmable to ramp in increments of 0.125 db at the rate controlled by the szc[1:0] bits in the digital volume control register. see ?transition control (address 06h)? on page 44. each output can be independently muted via mute control bits in the register ?dac channel mute (address 07h)? on page 45. when enabled, each aoutx_mute bit attenuates the corre- sponding dac to its maximum value (-127.5 db). when the aoutx_mute bit is disabled, the corresponding dac returns to the attenuation level set in the volume control register. the at- tenuation is ramped up and down at the rate specified by the szc[1:0] bits. 5.3.4 de-emphasis filter the cs42432 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 khz. the filter response is shown in figure 12. the de-emphasis feature is included to accommodate au- dio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. aoutx+ aoutx- full-scale differential output level = (aoutx+) - (aoutx-) = 6.5 v pp = 2.3 v rms 4.125 v 2.5 v 0.875 v 5.0 v 4.125 v 2.5 v 0.875 v va figure 11. full-scale output
ds673pp2 31 de-emphasis is only avail able in single speed mode. please see ?dac de-emphasis control (dac_dem)? on page 43 for de-emphasis control. 5.4 system clocking the codec serial audio interface ports operate as a slave and accept externally generated clocks. the codec requires external generation of the master clock (mclk). the frequency of this clock must be an integer multiple of, and synchronous with, the system sample rate, fs. hardware mode the allowable ratios include 256fs and 512fs in single-speed mode and 256fs in double-speed mode. the frequency of mclk must be specified using the mfreq (pin 3). see table 3 below for the required frequency range. software mode the frequency range of mclk must be specified usi ng the mfreq bits in register ?mclk frequency (mfreq[2:0])? on page 42. 5.5 codec digital interface the adc and dac serial ports operate as a slave and support the tdm digital interface formats with vary- ing bit depths from 16 to 32 as shown in figure 13 . data is clocked out of the adc on the falling edge of sclk and clocked into the dac on the rising edge. tdm is the only interface supported in hardware and software mode. 5.5.1 tdm data is received most significant bit (msb) firs t, on the second rising edge of the sclk occurring after an fs rising edge. all data is valid on the rising edge of sclk. the ain1 msb is transmitted early but is guaranteed valid for a specified time after sclk rises. all other bits are transmitted on the falling edge of sclk. each time slot is 32 bits wide, with the valid data sample left justified within the time slot. valid data lengths are 16, 18, 20, or 24. sclk must operate at 256fs. fs identifies the start of a new frame and is equal to the sample rate, fs. ratio (xfs) mfreq description ssm dsm qsm 0 1.5360 mhz to 12.8000 mhz 256 n/a n/a 1 2.0480 mhz to 25.6000 mhz 512 256 n/a table 3. mclk frequency settings gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 12. de-emphasis curve
32 ds673pp2 fs is sampled as valid on the rising sclk edge pr eceding the most significant bit of the first data sample and must be held valid for at least 1 sclk period. note: the adc does not meet the timing requir ements for proper operation in quad-speed mode. 5.5.2 i/o channel allocation digital input/output interface format analog output/input channel allocation from/to digital i/o dac_sdin tdm aou t 1,2,3,4,5,6 adc_sdout tdm ain 1,2,3,4 (2 addit ional channels from aux_sdin) table 4. serial audio interface channel allocations sclk fs 256 clks bit or word wide aout6 lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb dac_sdin aout1 aout4 aout2 aout5 aout3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks - lsb msb lsb msb - 32 clks 32 clks msb lsb - lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb adc_sdout ain1 ain4 ain2 - ain3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks aux2 lsb msb lsb msb aux1 32 clks 32 clks msb figure 13. tdm serial audio format
ds673pp2 33 5.6 aux port digital interface formats these serial data lines are used when supporting th e tdm mode of operation with an external adc or s/pdif receiver attached. the aux serial port operat es only as a clock master. the aux_sclk will op- erate at 64xfs, where fs is equal to the adc sample rate (fs on the tdm interface). if the aux_sdin signal is not being used, it should be tied to agnd via a pull-down resistor. hardware mode the aux port will only operate in the left justified di gital interface format and supports bit depths ranging from 16 to 24 bits (see figure 15 on page 33 for timing relationship between aux_lrck and aux_sclk). software mode the aux port will operate in either the left justified or i2s digital interface format with bit depths ranging from 16 to 24 bits. settings for the aux port are made through the register ?miscellaneous control (ad- dress 04h)? on page 42. 5.6.1 i2s 5.6.2 left justified aux_lrck aux_sclk msb lsb msb lsb aux1 left channel right channel aux_sdin aux2 msb figure 14. aux i2s format aux_lrck aux_sclk msb lsb msb lsb aux1 left channel right channel aux_sdin aux2 msb figure 15. aux left justified format
34 ds673pp2 5.7 control port d escription and timing the control port is used to access the registers, in software mode, allowing the cs42432 to be configured for the desired operational modes and formats. the operat ion of the control port may be completely asyn- chronous with respect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port has 2 modes: spi and i2c, with the cs42432 acting as a slave device. spi mode is se- lected if there is a high to low transition on the ad0/cs pin, after the rst pin has been brought high. i2c mode is selected by connecting the ad0/cs pin through a resistor to vlc or dgnd, thereby permanently selecting the desired ad0 bit address state. 5.7.1 spi mode in spi mode, cs is the cs42432 chip select signal, cclk is the control port bit clock (input into the cs42432 from the microcontroller), cdin is t he input data line from the microcontroller, cd- out is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 16 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and must be 1001111. the eighth bit is a read/write indicator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next eight bits are the data which will be placed in to the register designated by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? resistor, if desired. there is a map auto increment capability, enabled by the incr bit in the map register. if incr is a zero, the map will stay constant for successive read or writes. if incr is set to a 1, the map will autoincrement after each byte is read or wri tten, allowing block reads or writes of successive registers. to read a register, the map has to be set to the correct address by executing a partial write cycle which finishes (cs high) immediately after the map byte. the map auto increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the ad- map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 1001111 1001111 map = memory address pointer, 8 bits, msb first high impedance figure 16. control port timing in spi mode
ds673pp2 35 dressed register (cdout will leave the high impedance state). if the map auto increment bit is set to 1, the data for successive registers will appear consecutively. 5.7.2 i 2 c mode in i2c mode, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two le ast significant bits of the chip ad- dress and should be connected through a resistor to vlc or dgnd as desired. the state of the pins is sensed while the cs42432 is being reset. the signal timings for a read and write cycle are shown in figure 17 and figure 18. a start con- dition is defined as a falling transition of sda wh ile the clock is high. a stop condition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the cs42432 after a start condi tion consists of a 7 bit chip address field and a r/w bit (high for a read, low for a write). the upper 5 bits of the 7-bit address field are fixed at 10010. to communicate with a cs42432, the chip addr ess field, which is the first byte sent to the cs42432, should match 10010 followed by th e settings of the ad1 and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects the register to be read or written. if the operation is a read, the con- tents of the register pointed to by the map will be output. setting the auto increment bit in map allows successive reads or writes of consecut ive registers. each byte is separated by an ac- knowledge bit. the ack bit is output from the cs42 432 after each input byte is read, and is input to the cs42432 from the microcontroller after each transmitted byte. since the read operation can not set the map, an aborted write operation is used as a preamble. as shown in figure 18, the write operation is aborted after the acknowledge for the map byte by sending a stop condition. the following pseudoc ode illustrates an aborted write operation fol- lowed by a read operation. send start condition. send 10010xx0 (chip address & write operation). receive acknowledge bit. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 ad1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 17. control port timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 ad1 ad0 0 sda 1 0 0 1 0 ad1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 18. control port timing, i2c read
36 ds673pp2 send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 10010xx1(chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto-increment bit in the map allows successive reads or writes of consecutive reg- isters. each byte is separated by an acknowledge bit. 5.8 recommended power-up sequence 5.8.1 hardware mode 1) hold rst low until the power supply and hardware cont rol pins are stable. in this state, the control port is reset to its default settings and vq will remain low. 2) bring rst high. the device will initially be in a low power state with vq low. 3) start mclk to the appropriate frequency, as discussed in section 5.4 on page 31. 4) the device will initiate the hardware mode power up sequence. all features will default to the hardware mode defaults as listed in table 2 on page 26 according to the hardware mode control pins. vq will quick-charge to approximately va/2 and the analog output bias will clamp to vq. 5) apply lrck, sclk and sdin. following appro ximately 2000 sample periods, the device is initialized and ready for normal operation. note: during the h/w mode power up sequence, t here must be no transitions on any of the hardware control pins. 5.8.2 software mode 1) hold rst low until the power supply is stable. in this state, the control port is reset to its de- fault settings and vq will remain low. 2) bring rst high. the device will initially be in a low power state with vq low. all features will default as described in the ?register quick reference? on page 38. 3) perform a write operation to the power co ntrol register (?power control (address 02h)? on page 41) to set bit 0 to a ?1?b. this will place the device in a power down state. 4) load the desired register settings while keeping the pdn bit set to ?1?b. 5) start mclk to the appropriate frequency, as discussed in section 5.4 on page 31. the device will initiate the software mode power up sequence. 6) set the pdn bit in the power control register to ?0?b. 7) apply lrck, sclk and sdin. following appro ximately 2000 sample periods, the device is initialized and ready for normal operation. 5.9 reset and power-up it is recommended that reset be activated if the an alog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.
ds673pp2 37 the delta-sigma modulators settle in a matter of mi croseconds after the analog section is powered, either through the application of power or by setting the rst pin high. however, the voltage reference will take much longer to reach a final value due to the presenc e of external capacitance on the filt+ pin. a time delay of approximately 400 ms is required after applying power to the device or after exiting a reset state. during this voltage reference ramp delay, all serial ports and dac outputs will be automatically muted. 5.10 power supply, groun ding, and pcb layout as with any high resolution converter, the cs42432 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figures 1 to 2 show the recommended power arrangements, with va connected to clean supplies. vd, which powers the digital circuitry, may be run from the system logic supply. extensive use of power and ground planes, ground plane fill in unused areas and surface mount decou- pling capacitors are recommended. dec oupling capacitors should be as near to the pins of the cs42432 as possible. the low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the cs42432 to minimize inductance effects. all signals, especially clocks, should be kept away from the filt+, vq pins in order to avoid unwanted coupling into the modulators. the filt+ and vq decoupling capacitors, particularly the 0.1 f, must be positioned to minimize the elec- trical path from filt+ and agnd. the cdb42438 eval uation board demonstrates the optimum layout and power supply arrangements. for optimal heat dissipation from the package, it is recommended that the area directly under the part be filled with copper and tied to the ground plane. the us e of vias connecting the topside ground to the back- side ground is also recommended.
38 ds673pp2 6 register quick reference software mode register defaults are as shown. note : the default value in all ?reserved? registers must be preserved. addr function 7 6 5 4 3 2 1 0 01h id chip_id3 chip_id2 chip_id1 chip_id0 rev_id3 rev_id2 rev_id1 rev_id0 p40 default 00000001 02h power con- trol reserved pdn_adc2 pdn_adc1 reserved pdn_dac3 pdn_dac2 pdn_dac1 pdn p41 default 00000000 03h functional mode reserved reserved reserved reserved mfreq2 mfreq1 mfreq0 reserved p42 default 11110000 04h misc control freeze aux_dif reserved re served reserved reserved reserved reserved p42 default 00110110 05h adc control (w/dac_dem) adc1-2_hpf freeze reserved dac_dem adc1 single adc2 single reserved reserved reserved p43 default 00000000 06h transition control dac_sng vol dac_szc1 dac_szc0 amute mute adc_sp adc_sng vol adc_szc1 adc_szc0 p44 default 00010000 07h channel mute reserved reserved aout6 mute aout5 mute aout4 mute aout3 mute aout2 mute aout1 mute p45 default 0 0 0 0 0 0 0 0 08h vol. control aout1 aout1 vol7 aout1 vol6 aout1 vol5 aout1 vol4 aout1 vol3 aout1 vol2 aout1 vol1 aout1 vol0 p45 default 00000000 09h vol. control aout2 aout2 vol7 aout2 vol6 aout2 vol5 aout2 vol4 aout2 vol3 aout2 vol2 aout2 vol1 aout2 vol0 p45 default 00000000 0ah vol. control aout3 aout3 vol7 aout3 vol6 aout3 vol5 aout3 vol4 aout3 vol3 aout3 vol2 aout3 vol1 aout3 vol0 p45 default 00000000 0bh vol. control aout4 aout4 vol7 aout4 vol6 aout4 vol5 aout4 vol4 aout4 vol3 aout4 vol2 aout4 vol1 aout4 vol0 p45 default 00000000 0ch vol. control aout5 aout5 vol7 aout5 vol6 aout5 vol5 aout5 vol4 aout5 vol3 aout5 vol2 aout5 vol1 aout5 vol0 p45 default 00000000 0dh vol. control aout6 aout6 vol7 aout6 vol6 aout6 vol5 aout6 vol4 aout6 vol3 aout6 vol2 aout6 vol1 aout6 vol0 p45 default 00000000 0eh reserved reserved reserved reserved res erved reserved reserved reserved reserved default 00000000 0fh reserved reserved reserved reserved res erved reserved reserved reserved reserved default 00000000 10h dac chan- nel invert reserved reserved inv_aout6 inv_aout5 in v_aout4 inv_aout3 inv_aout2 inv_aout1 p46 default 00000000
ds673pp2 39 11h vol. control ain1 ain1 vol7 ain1 vol6 ain1 vol5 ain1 vol4 ain1 vol3 ain1 vol2 ain1 vol1 ain1 vol0 p45 default 00000000 12h vol. control ain2 ain2 vol7 ain2 vol6 ain2 vol5 ain2 vol4 ain2 vol3 ain2 vol2 ain2 vol1 ain2 vol0 p46 default 00000000 13h vol. control ain3 ain3 vol7 ain3 vol6 ain3 vol5 ain3 vol4 ain3 vol3 ain3 vol2 ain3 vol1 ain3 vol0 p45 default 00000000 14h vol. control ain4 ain4 vol7 ain4 vol6 ain4 vol5 ain4 vol4 ain4 vol3 ain4 vol2 ain4 vol1 ain4 vol0 p46 default 00000000 15h reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 00000000 16h reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 00000000 17h adc chan- nel invert reserved reserved reserved reserved inv_a4 inv_a3 inv_a2 inv_a1 p46 default 00000000 18h reserved reserved reserved reserved rese rved reserved reserved reserved reserved default 00000000 19h status reserved reserved reserved clk error reserved adc2 ovfl adc1 ovfl p47 default 000xxxxx 1ah status mask reserved reserved reserved clk error_m reserved adc2 ovfl_m adc1 ovfl_m p47 default 00000000 addr function 7 6 5 4 3 2 1 0
40 ds673pp2 7 register description all registers are read/write except for the i.d. and revi sion register and interrup t status register which are read only. see the following bit definition tables for bit assignment informatio n. the default state of each bit after a power-up sequence or reset is listed in each bit description. 7.1 memory address pointer (map) not a register 7.1.1 increment(incr) default = 1 function: memory address pointer auto increment control 0 - map is not incremented automatically. 1 - internal map is automatically in cremented after each read or write. 7.1.2 memory address pointer (map[6:0]) default = 0000001 function: memory address pointe r (map). sets the re gister address that will be read or written by the control port. 7.2 chip i.d. and revi sion register (ad dress 01h) (read only) 7.2.1 chip i.d. (chip_id[3:0]) default = 0000 function: i.d. code for the cs42432. permanently set to 0000. 7.2.2 chip revisi on (rev_id[3:0]) default = 0001 function: cs42432 revision level. revision a is coded as 0001. 76543210 incr map6 map5 map4 map3 map2 map1 map0 76543210 chip_id3 chip_id2 chip_id1 chip_id0 rev_id3 rev_id2 rev_id1 rev_id0
ds673pp2 41 7.3 power control (address 02h) 7.3.1 power down adc pairs(pdn_adcx) default = 0 0 - disable 1 - enable function: when enabled, the respective a dc channel pair (adc1 - ain1/ain2; and adc2 - ain3/ain4) will re- main in a reset state. 7.3.2 power down dac pairs (pdn_dacx) default = 0 0 - disable 1 - enable function: when enabled, the respective dac channel pair (dac1 - aout1/aout2; dac2 - aout3/aout4; and dac3 - aout5/aout6) will remain in a reset state. it is advise d that any change of these bits be made while the dacs are muted or the power down bit (pdn) is en abled to eliminate the possibility of audible artifacts. 7.3.3 power down (pdn) default = 0 0 - disable 1 - enable function: the entire device will enter a low-powe r state when this function is enabled. the contents of the con- trol registers are retained in this mode. 76543210 reserved pdn_adc2 pdn_adc1 reserved pdn_dac3 pdn_dac2 pdn_dac1 pdn
42 ds673pp2 7.4 functional mo de (address 03h) 7.4.1 mclk frequency (mfreq[2:0]) default = 000 function: sets the appropriate frequency for the supplied mc lk. for tdm operation, sclk must equal 256fs. mclk can be equal to or greater than sclk. 7.5 miscellaneous control (address 04h) 7.5.1 freeze controls (freeze) default = 0 function: this function will freeze the previous settings of , and allow modifications to be made to the channel mutes, the dac and adc volume co ntrol/channel invert registers wit hout the changes taking effect until the freeze is disabled. to have multiple changes in these contro l port registers take effect si- multaneously, enable the freeze bit, make a ll register changes, then disable the freeze bit. 7.5.2 auxiliary digital interface format (aux_dif) default = 0 0 - left justified 1 - i2s function: this bit selects the digital interface format used for the aux serial port. the required relationship be- tween the left/right clock, serial cl ock and serial data is defined by the digital interface format and the options are detailed in figures 14-15. 76543210 reserved reserved reserved reserved mfreq2 mfreq1 mfreq0 reserved ratio (xfs) mfreq2 mfreq1 mfreq0 d escription ssm dsm qsm 000 1.0290 mhz to 12.8000 mhz 256 n/a n/a 001 1.5360 mhz to 19.2000 mhz 384 n/a n/a 010 2.0480 mhz to 25.6000 mhz 512 256 n/a 011 3.0720 mhz to 38.4000 mhz 768 384 n/a 1xx 4.0960 mhz to 51.2000 mhz 1024 512 256 table 5. mclk frequency settings 76543210 freeze aux_dif reserved reserved reserved reserved reserved reserved
ds673pp2 43 7.6 adc control & dac de -emphasis (address 05h) 7.6.1 adc1-2 high pass filter freeze (adc1-2_hpf freeze) default = 0 function: when this bit is set, the intern al high-pass filter will be disabled for adc1 and adc2.the current dc offset value will be frozen and conti nue to be subtracted from the c onversion result. see ?adc digital filter characteristics? on page 15. 7.6.2 dac de-emphasis control (dac_dem) default = 0 0 - no de-emphasis 1 - de-emphasis enabled (auto-detect fs) function: enables the digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 khz. de-e mphasis will not be e nabled, regardless of this register setting, at any other sample rate. 7.6.3 adc1 single-ended mode (adc1 single) default = 0 0 - disabled; differential input to adc1 1 - enabled; single-ended input to adc1 function: when enabled, this bit allows the user to apply a single-ended input to the positive terminal of adc1. +6 db digital gain is automatically applied to the serial audio data of adc1. the negative leg must be driven to the common mode of the adc. see figu re 20 on page 49 for a graphical description. 7.6.4 adc2 single-ended mode (adc2 single) default = 0 0 - disabled; differential input to adc2 1 - enabled; single-ended input to adc2 function: when enabled, this bit allows the user to apply a single-ended input to the positive terminal of adc2. +6 db digital gain is automatically applied to the serial audio data of adc2. the negative leg must be driven to the common mode of the adc. see figure 20 on page 49 for a graphical description. 76543210 adc1-2_hpf freeze reserved dac_dem adc1 single adc2 single reserved reserved reserved
44 ds673pp2 7.7 transition cont rol (address 06h) 7.7.1 single volume contro l (dac_sngvol, adc_sngvol) default = 0 function: the individual channel volume levels are independent ly controlled by their re spective volume control registers when this function is disabled. when enab led, the volume on all ch annels is determined by the aout1 and ain1 volume control register and the other volume control registers are ignored. 7.7.2 soft ramp and zero cross co ntrol (adc_szc[1:0] , dac_szc[1:0]) default = 00 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is selected all volume level chan ges will take effect imme diately in one step. zero cross zero cross enable dictates that signal level chan ges, either by gain change s, attenuation changes or muting, will occur on a signal zero crossing to mini mize audible artifacts. the requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a ze ro crossing. the zero cross function is independent- ly monitored and implemented for each channel. soft ramp soft ramp allows level changes, ei ther by gain changes, attenuation changes or muting, to be imple- mented by incrementally ramping, in 1/8 db steps, fr om the current level to th e new level at a rate of 1 db per 8 left/right clock periods. soft ramp on zero crossing soft ramp and zero cross enable dictates that si gnal level changes, either by gain changes, atten- uation changes or muting, will occur in 1/8 db steps and be implemen ted on a signal zero crossing. the 1/8 db level change will occur a fter a timeout period between 51 2 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the sign al does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 7.7.3 auto-mute (amute) default = 1 0 - disabled 1 - enabled function: 76543210 dac_sngvol dac_szc1 dac_szc0 amute mute adc_sp adc_sngvol adc_szc1 adc_szc0
ds673pp2 45 the digital-to-analog converters of the cs42432 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. a singl e sample of non-static data will release the mute. detection and muting is done independently for ea ch channel. the quiescent voltage on the output will be retained during the mute pe riod. the muting function is affe cted, similar to volume control changes, by the soft and zero cross bits (szc[1:0]). 7.7.4 mute adc serial port (mute adc_sp) default = 0 0 - disabled 1 - enabled function: when enabled, the adc serial port will be muted. 7.8 dac channel mu te (address 07h) 7.8.1 independent channel mute (aoutx_mute) default = 0 0 - disabled 1 - enabled function: the respective digital-to-analog converter outputs of the cs42432 will mute when enabled. the qui- escent voltage on the outp uts will be retained. the muting function is affe cted by the dac soft and zero cross bits (dac_szc[1:0]). 7.9 aoutx volume control (a ddresses 08h-0d) 7.9.1 volume control (aoutx_vol[7:0]) default = 00h function: the aoutx volume control registers allow independent setting of the signal levels in 0.5 db incre- ments from 0 db to -127.5 db. volume settings are decoded as shown in table 6. the volume chang- es are implemented as dictated by the soft and ze ro cross bits (dac_szc[1 :0]). all volume settings less than -127.5 db are equivalent to enabling the aoutx_mute bit for the given channel. 76543210 reserved reserved aout6_mute aout5_mute aout4_mute aout3_mute aout2_mute aout1_mute 76543210 aoutx_vol7 aoutx_vol6 aoutx_vol5 aoutx_vol4 aoutx_vol3 aoutx_vol2 aoutx_vol1 aoutx_vol0
46 ds673pp2 7.10 dac channel in vert (address 10h) 7.10.1 invert signal polarity (inv_aoutx) default = 0 0 - disabled 1 - enabled function: when enabled, these bits will invert the sign al polarity of their respective channels. 7.11 ainx volume cont rol (address 11h-14h) 7.11.1 ainx volume co ntrol (ainx_vol[7:0]) default = 00h function: the level of ain1 - ain6 can be adjusted in 0.5 db increments as dictated by the adc soft and zero cross bits (adc_szc[1:0]) from +24 to -64 db. levels are decoded in two?s complement, as shown in table 7. binary code volume setting 00000000 0 db 00101000 -20 db 01010000 -40 db 01111000 -60 db 10110100 -90 db table 6. example aout volume settings 76543210 reserved reserved inv_aout6 inv_aout5 in v_aout4 inv_aout3 inv_aout2 inv_aout1 76543210 ainx_vol7 ainx_vol6 ainx_vol5 ainx_vol4 ainx_vol3 ainx_vol2 ainx_vol1 ainx_vol0 binary code volume setting 0111 1111 +24 db 0011 0000 +24 db 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1 db 1000 0000 -64 db table 7. example ain volume settings
ds673pp2 47 7.12 adc channel in vert (address 17h) 7.12.1 invert signal polarity (inv_ainx) default = 0 0 - disabled 1 - enabled function: when enabled, these bits will invert the sign al polarity of their respective channels. 7.13 status (addre ss 19h) (read only) for all bits in this register, a ?1? means the associated error condition has occurred at least once since the register was last read. a?0? means the associated error condition has not occurred since the last reading of the register. reading the register resets all bits to 0. status bits that are masked off in the associated mask register will always be ?0? in this register. 7.13.1 clock error (clk error) default = x function: indicates an invalid mclk to fs ra tio. this status flag is set to ?level active mode? and becomes ac- tive during the error condition. see ?system clocking? on page 31 for valid clock ratios. 7.13.2 adc overflow (adcx_ovfl) default = x function: indicates that there is an over-range condition any where in the cs42432 adc signal path of each of the associated adc?s. 7.14 status mask (address 1ah) default = 0000 function: the bits of this register serve as a mask for the error sources found in the register ?status (address 76543210 reserved reserved reserved reserved inv_ain4 inv_ain3 inv_ain2 inv_ain1 76543210 reserved reserved reserved reserved clk error reserved adc2_ovfl adc1_ovfl 76543210 reserved reserved reserved reserved clk error_m reserved adc2_ovfl_m adc1_ovfl_m
48 ds673pp2 19h) (read only)? on page 47. if a mask bit is set to 1, the error is unmasked, meaning that its occur- rence will affect the status register. if a mask bit is se t to 0, the error is mask ed, meaning t hat its oc- currence will not affect st atus register. the bit positions align wit h the corresponding bits in the status register.
ds673pp2 49 8 appendix a: external filters 8.1 adc input filter the analog modulator samples the input at 6.144 mhz (internal mclk=12.288 mhz). the digital filter will reject signals within the stopband of the filter. however, there is no rejection for input signals which are multiples of the digital passband frequency (n 6.144 mhz), where n=0,1,2,... refer to figures 19 and 20 for a recommended analog input filter that will attenuate any noise energy at 6.144 mhz, in addition to providing the optimum source impedance for the modulators. refer to figures 21 and 22 for low cost, low component count passive input filters. the use of capacitors which have a large voltage coefficient (such as general-purpose ceramics) must be avoid ed since these can degrade signal linearity. va + + - - 4.7 f 100 k ? 10 k ? 100 k ? 100 k ? 0.1 f 100 f 470 pf 470 pf c0g c0g 634 ? 634 ? 634 ? 91 ? 91 ? 2700 pf c0g 332 ? ainx+ ainx- adc1-2 figure 19. single to differ ential active input filter - + 470 pf c0g 634 ? 91 ? 2700 pf c0g 4.7 f 100 k ? 100 k ? 100 k ? va 4.7 f ain1+,2+,3+,4+ ain1-,2-,3-,4- adc1-2 figure 20. single-ende d active input filter
50 ds673pp2 8.1.1 passive input filter the passive filter implementation shown in figure 21 will attenuate any noise energy at 6.144 mhz but will not provide optimum sour ce impedance for the adc modulators. full analog performance will therefore not be realized using a passive filter. figure 21 illustrates the unity gain, passive input filter solution. in this topology the distortion performance is affected, but the dynamic range performance is not limited. 8.1.2 passive input fi lter w/attenuation some applications may require signal attenuation prior to the adc. the full-scale input voltage will scale with the analog power supply voltage. for va = 5.0 v, the full-scale input voltage is approximately 2.8 vpp, or 1 vrms (most consum er audio line-level outputs range from 1.5 to 2vrms). figure 22 shows a passive input filter with 6 db of signal attenuation. due to the relatively high input impedance on the analog inputs, the full dist ortion performance cannot be realized. also, the resistor divider circuit will determine the inpu t impedance into the input filter. in the circuit shown in figure 22, the inpu t impedance is approximately 5 k ?. by doubling the resistor values, the input impedance will increase to 10 k ?. however, in this case the distortion performance will drop due to the increase in series resistance on the analog inputs. 2700 pf c0g 10 f 100 k ? 150 ? ain1+,2+,3+,4+ ain1-,2-,3-,4- adc1-2 4.7 f figure 21. passive input filter 2700 pf c0g 10 f 2.5 k ? ain1+,2+,3+,4+ ain1-,2-,3-,4- adc1-2 4.7 f 2.5 k ? figure 22. passive input filter w/attenuation
ds673pp2 51 8.2 dac output filter the cs42432 is a linear phase design and does not in clude phase or amplitude compensation for an ex- ternal filter. therefore, the dac system phase and amplitude response will be dependent on the external analog circuitry. shown below is the recommended active and passive output filters. aoutx + aoutx - - + 390 pf c0g 562 ? 22 f 4.75 k ? 1800 pf c0g 887 ? 2.94 k ? 5.49 k ? 1.65 k ? 1.87 k ? 22 f 1200 pf c0g 5600 pf c0g 47.5 k ? dac1-3 figure 23. active analog output filter aoutx+ 3.3 f c 560 ? + 10 k ? r ext r ext + 560 c= 4 f s r ext 560 dac1-3 figure 24. passive analog output filter
52 ds673pp2 9 appendix b: adc filter plots -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db ) figure 25. ssm stopband rejection figure 26. ssm transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normalized to fs) amplitude (db) figure 27. ssm transition band (detail) figure 28. ssm passband ripple -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db ) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 29. dsm stopband rejection figure 30. dsm transition band
ds673pp2 53 ? -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (norm alized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (normalized to fs) amplitude (db ) figure 31. dsm transition band (det ail) figure 32. dsm passband ripple
54 ds673pp2 10 appendix c: dac filter plots figure 33. ssm stopband rejection figure 34. ssm transition band figure 35. ssm transition band (detail) figure 36. ssm passband ripple -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.6 0 frequency (normalized to fs) amplitude db figure 37. dsm stopband rejection figure 38. dsm transition band
ds673pp2 55 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.5 5 frequency (normalized to fs) amplitude db -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.5 0 frequency (normalized to fs) amplitude db figure 39. dsm transition band (detail) figure 40. dsm passband ripple 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) figure 41. qsm stopband rejection figure 42. qsm transition band 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) 0.4 0.45 0.5 0.55 0.6 0.65 0.7 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 amplitude (db) frequency(normalized to fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 amplitude (db) frequency(normalized to fs) figure 43. qsm transition band (det ail) figure 44. qsm passband ripple
56 ds673pp2 11 parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise rati o measurement over the specified band width made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the di stortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic indu stries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 hz to 20 khz), including di stortion components. expres sed in decibels. measured at -1 and -20 dbfs as sug gested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right chan nel pairs. measured for each channel at the con- verter's output with no signal to the input under te st and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channel pairs. units in decibels. gain error the deviation from the nominal full-scale ana log output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111... 111 to 000...000) from the ideal. units in mv.
ds673pp2 57 12 references 1) cirrus logic, audio qualit y measurement specification , version 1.0, 1997. http://www.cirrus.com/products/papers/meas/meas.html 2) cirrus logic, an18: layout and design rules for data converters and ot her mixed signal devices , version 6.0, february 1998. 3) cirrus logic, techniques to measure and maxi mize the performance of a 120 db, 96 khz a/d con- verter integrated circuit , by steven harris, steven green and ka leung. presented at the 103rd conven- tion of the audio engineerin g society, september 1997. 4) cirrus logic, a stereo 16-bit delta-sigma a/d converter for digital audio , by d.r. welland, b.p. del signore, e.j. swanson, t. tanaka, k. hamashita, s. hara, k. takasuka. paper presented at the 85th convention of the audio engineer ing society, november 1988. 5) cirrus logic, the effects of sampling clock jitt er on nyquist sampling anal og-to-digital converters, and on oversampling delta sigma adc's , by steven harris. paper presented at the 87th convention of the audio engineering society, october 1989. 6) cirrus logic, an 18-bit dual-channel oversampling delta-sigma a/d converter, with 19-bit mono ap- plication example , by clif sanchez. paper presented at the 87th convention of the audio engineering so- ciety, october 1989. 7) cirrus logic, how to achieve optimum perfor mance from delta-sigma a/d and d/a converters ,by steven harris. presented at the 93rd convention of the audio engineering society, october 1992. 8) cirrus logic, a fifth-order delta-sigma modulator with 110 db audio dynamic range , by i. fujimori, k. hamashita and e.j. swanson. paper presented at the 93rd convention of the audio engineering so- ciety, october 1992. 9) philips semiconductor, the i2c-bus specification: version 2.1 , january 2000. http://www.semicon- ductors.philips.com
58 ds673pp2 13 package information 13.1 thermal characteristics inches millimeters dim min nom max min nom max a --- --- 0.096 --- --- 2.45 a1 0.000 --- 0.010 0.00 --- 0.25 b 0.009 --- 0.016 0.22 --- 0.40 d --- 0.519 --- --- 13.20 bsc --- d1 --- 0.394 --- --- 10.00 bsc --- e --- 0.519 --- --- 13.20 bsc --- e1 --- 0.394 --- --- 10.00 bsc --- e* --- 0.026 --- --- 0.65 bsc --- l 0.029 0.035 0.041 0.73 0.88 1.03 0.00 4 7.00 0.00 4 7.00 * nominal pin pitch is 0.65 mm controlling dimension is mm. jedec designation: ms022 parameter symbol min typ max units junction to ambient thermal impedance 2 layer board 4 layer board ja ja - - 47 38 - - c/watt c/watt e1 e d1 d 1 e l b a1 a 52l mqfp package drawing
ds673pp2 59 14 ordering information product description package pb-free grade temp range container order # cs42432 4-in, 6-out, tdm codec for surround sound apps 52l-mqfp yes commercial -10 to +70 c rail cs42432-cmz tape & reel CS42432-CMZR automotive -40 to +85 c rail cs42432-dmz tape & reel cs42432-dmzr cdb42438 cs42432 evaluation board - - - - - cdb42438
60 ds673pp2 15 revision history revision date changes a1 october 2004 initial release pp1 january 2005 initial preliminary pr oduct (pp) release subject to legal notice below. added pin numbers to ?typical connection diagram (software mode)? on page 10 and ?typical connection diagram (hardware mode)? on page 11 . changed adc double-speed mode parameters. see note 2 on page 12 and note 18 on page 21 . changed adc passband ripple maximum specifications for ssm, dsm & qsm in section ?characteristics and specifications? beginning on page 12. changed dac frequency response specifications for ssm, dsm & qsm in section ?characteristics and s pecifications? beginning on page 12. removed adc quad-speed mode feature. see note 19 on page 21 . added section ?de-emphasis filter? on page 30 . corrected section ?tdm? on page 31 . changed ain1-6 volume control range from (+12 db to -115.5 db) to (+24 db to -64 db) in register ?ainx volume control (ainx_vol[7:0])? on page 46 . removed the register ?status control (address 18h)?. see ?clock error (clk error)? on page 47 and ?adc overflow (adcx_ovfl)? on page 47 for the active mode setting. pp2 february 2005 corrected figures 20-22. added section ?ordering information? on page 59 . table 8. revision history
ds673pp2 61 important notice ?preliminary? product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all product s are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnificat ion, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the bas is for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by f urnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or othe r intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). cirrus products are not designed, autho- rized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security devices, life support products or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, incl uding the implied warranties of merchantability and fit- ness for particular purpose, with regard to any cirrus pr oduct that is used in such a manner. if the customer or customer's customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, di rectors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a registered trademark of motorola, inc. contacting cirrus logic support for all product questions and inquiries c ontact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com/
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